Using an ICP-based strip system to perform resist and barrier-layer removal in copper low-k processes

摘要

The successful integration of copper interconnects and low-k dielectrics in dual-damascene processes has been a critical, but difficult, step in the development of IC technology. The new materials used in interconnect layers are essential for achieving the higher-speed operations that are required for advanced computing and communications applications. Because copper is a better conductor than aluminum and the interline capacitance of low-k materials is lower than that of silicon dioxide, copper/low-k technology reduces resistance-capacitance (RC) delay for sig- nals and accelerates the switching of logic gates in the circuit. One part of the copper/low-k integration process, stripping photoresist and cleaning wafers without damaging the low-k materials, has been a signifi- cant challenge. Advanced semiconductor fabs have met this challenge in production, and work is proceeding on the development of next-generation ultra-low-k dielectrics—particularly nanoporous materials—to further reduce the dielectric constant.