Meeting the Nanoscale Device Fabrication Challenge

摘要

Over the past year, many chip manufacturers have introduced their 90-nm process technologies and ramp plans, and several have begun volume production. Crossing the 100-nm line marks the entry into nanometer-scale devices, a world where various second-order effects become major technology issues. These new challenges have started to dominate device behavior and have a negative impact on fabrication. A few of these problems have emerged as serious integration limiters, threatening to diminish the performance benefits that device scaling has provided up to this point.