Multilevel thin film packaging: applications and processes for highperformance systems

摘要

IBM has developed and implemented multilayer thin films (MLTF) for both high end and cost-performance systems since the early 1980's. Copper-polymer and aluminum-polymer multilayer thin films have been implemented on silicon, alumina, and glass-ceramic substrates. The various MLTF implementations are: Two layers of Cu-polyimide interconnection on dry pressed alumina for single and dual chip applications, using wet etch of polyimide and subtractive etching of Cr-Cu-Cr for wiring. One to two layers of planar Cu-polyimide interconnection on alumina and glass-ceramic multichip modules for redistribution of chip I/O's to the ceramic vias, using laser ablation for via definition, subtractive etching of Cr-Cu-Cr for wiring definition, and liftoff for bonding pad definition. Four layers of Al-polyimide multichip interconnection on silicon substrates, using reactive ion etching for via definition, subtractive etching of aluminum for wiring definition, and evaporation through a mask for bonding pad definition. Four to five layers of planar Cu-polyimide interconnection on glass-ceramic substrates, using laser ablation for via definition, photosensitive polyimide (PSPI) lithography and blanket electroplating for wiring definition, and liftoff for bonding pad definition. Four or five layers of non-planar Cu-polyimide interconnection on alumina, silicon, and glass-ceramic substrates, using laser ablation or photosensitive polyimide lithography for via definition, additive electroplating or subtractive etching of Cu for wiring definition, and additive electroplating for bonding pad definition. In this paper we discuss the evolution of these thin film technologies as well as the process choices, their merits, and the reasoning behind the various choices