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The VLSI implementation of a high-resolution depth-sensing SoC based on active structured light

机译:基于有源结构光的高分辨率深度感应SoC的VLSI实现

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摘要

This paper presents the full VLSI implementation of a new high-resolution depth-sensing system on a chip (SoC) based on active infrared structured light, which estimates the 3D scene depth by matching randomized speckle patterns, akin to the Microsoft Kinect. We present a module to enhance the consistency of speckle patterns for robust matching, and hence improve the range of depth estimation. We present a simple and efficient hardware structure for a block-matching-based disparity estimation algorithm, which facilitates rapid generation of disparity maps in real time. For depth estimation from disparity maps, we propose a hardware friendly solution by producing a lookup table from a curve fitted to calculate and calibrate the depth value in a single step, which does not need to explicitly calibrate the parameters of the imaging sensors, such as the length of the baseline. We have implemented these ideas in an end-to-end SoC using FPGA. Compared with the Kinect, our depth-sensing SoC has wider effective ranging limit (0.6-4.5 m), and has an uppermost 1280 × 1024 processing capacity with 60 Hz frame frequency. Its depth resolution is 1 mm@0.82m. Our system is superior to Kinect in terms of operating range, processing frame rate, and resolution.
机译:本文介绍了基于主动红外结构光的新型高分辨率芯片上深度感应系统(SoC)的完整VLSI实现,该系统通过匹配类似于Microsoft Kinect的随机散斑图案来估计3D景深。我们提出了一个模块,以增强散斑图案的一致性,以进行鲁棒匹配,从而提高深度估计的范围。我们提出了一种基于块匹配的视差估计算法的简单而有效的硬件结构,它有助于实时快速生成视差图。对于根据视差图进行深度估计,我们提出了一种硬件友好的解决方案,即通过一条曲线生成一张查找表,该曲线适合在单个步骤中计算和校准深度值,而无需显式校准成像传感器的参数,例如基线的长度。我们已经使用FPGA在端到端SoC中实现了这些想法。与Kinect相比,我们的深度感应SoC具有更宽的有效范围限制(0.6-4.5 m),并具有60 Hz帧频的最高1280×1024处理能力。其深度分辨率为1 mm@0.82m。我们的系统在操作范围,处理帧速率和分辨率方面均优于Kinect。

著录项

  • 来源
    《Machine Vision and Applications》 |2015年第4期|533-548|共16页
  • 作者单位

    Institute of Artificial Intelligence and Robotics, Xi'an Jiaotong University, Xi'an, Shaanxi, China;

    Institute of Artificial Intelligence and Robotics, Xi'an Jiaotong University, Xi'an, Shaanxi, China;

    Department of Computer Science, Stevens Institute of Technology, Hoboken, NJ 07030, USA;

    Institute of Artificial Intelligence and Robotics, Xi'an Jiaotong University, Xi'an, Shaanxi, China;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Depth-sensing SoC; VLSI; Disparity map; Depth estimation; Dpeckle pattern;

    机译:深度感应SoC;超大规模集成电路视差图;深度估计;滴纹;

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