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首页> 外文期刊>Journal of Spacecraft Technology >Design, Development and Qualification of Surface Mount J-Lead Resistor-Capacitor Networks for Miniaturization of Space Electronics
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Design, Development and Qualification of Surface Mount J-Lead Resistor-Capacitor Networks for Miniaturization of Space Electronics

机译:用于太空电子小型化的表面贴装J引线电阻器-电容器网络的设计,开发和鉴定

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This paper presents design and development of innovative and highly miniaturized Resistor-Capacitor (RC)Networks using Thick film process technology with Surface mountable (SMT) J-Leads.The advantages of theseSMT RC Networks over standard through-hole mountable Single-in-Line (SIL) RC Networks are much smallersize,more portable and reduced weight.Three types of J-leaded SMT RC Networks have been developed,qualifiedand fabricated for On-Board Computer (OBC) of Attitude & Orbit Control Electronics (AOCE) subsystem anddelivered to EMISAT and HYSIS projects.Challenges faced during the development of these RC Networks andQualification tests performed to qualify the Advanced Processes and Products are presented in this paper.
机译:本文介绍了采用厚膜工艺技术和表面贴装(SMT)J引线的创新型和高度小型化的电阻器(RC)网络的设计和开发,这些SMT RC网络相对于标准通孔可安装单列直插式电源的优势(SIL)RC网络尺寸更小,更轻便,重量更轻。已开发出三种类型的J引线SMT RC网络,用于姿态和轨道控制电子(AOCE)子系统的车载计算机(OBC)并进行了验证和制造,并已交付给本文介绍了EMISAT和HYSIS项目。在开发这些RC网络和进行资格测试以验证先进工艺和产品的过程中面临的挑战。

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