Power and Speed-Efficient Code Transformation of Video Compression Algorithms for RISC Processors

摘要

Upcoming multi--media compression applications will require high memory bandwidth. In this paper, we estimate that a software reference implementation of an MPEG4 video decoder typically requires 200 Mtransfers/s to memory to decode 1 CIF (352 × 288) Video Object Plane (VOP) at 30 frames/s. This imposes a high penalty in terms of power but also performance. However, we also show that we can heavily improve on the memory transfers, without sacrificing speed (even gaining about 10/100 on cache misses and cycles for a DEC Alpha), by aggressive code transformations. For this purpose, we have manually applied an extended version of our data transfer and storage exploration (DTSE) methodology, which was originally developed for custom hardware implementations.