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首页> 外文期刊>Journal of Real-Time Image Processing >Energy-aware cache hierarchy assessment targeting HEVC encoder execution
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Energy-aware cache hierarchy assessment targeting HEVC encoder execution

机译:针对HEVC编码器执行的能量感知缓存层次评估

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摘要

This article presents a framework for assessing the behavior and energy impact of cache hierarchies when encoding HEVC on general-purpose processors. The memory energy estimation framework estimates energy consumption of cache hierarchies based on mathematical models combined with memory access profiling tools. The energy analysis of several cache hierarchies targeting HEVC encoders with different input parameters is also carried out. This article provides relevant information on the energy consumption of HEVC encoders by taking into account the different tradeoffs between energy efficiency, coding efficiency, and other important cache memory design parameters, such as miss rates and access latency. The first analysis explores cache performance for different specifications, such as capacity, line size. Results show that most of the energy is spent on reading operations (almost 73% on the first level cache), indicating that HEVC encoders could benefit from memory technologies with low reading energy costs. This analysis also pointed that increasing the capacity affects more the energy performance of the first level cache, which represents 34.78% (on average) more energy consumption than the last level cache. Based on this investigation, we report the most suited cache specifications for HEVC encoders for each video resolution. The second analysis discusses the impact of HEVC input parameters in cache performance, demonstrating that it is possible to save up to 30% of energy with a small increase of 2% in BD-BR. A comparative analysis between HM (HEVC model) and x265 (H.265 video codec) HEVC software models is presented, demonstrating that x265 is faster (speedup to 648x), and more cache efficient providing less memory energy (31.38% on average) compared to the HM implementation. The results obtained with the proposed framework indicate that the management of video encoding parameters combined with application-tuned cache specifications has a high potential to reduce energy consumption of video coding systems while keeping video quality.
机译:本文提供了一个框架,用于在通用处理器上编码HEVC时评估高速缓存层次结构的行为和能量影响。内存能量估计框架基于数学模型结合内存访问分析工具来估计高速缓存层次结构的能耗。还针对具有不同输入参数的针对HEVC编码器的几个缓存层次结构进行了能量分析。本文通过考虑能量效率,编码效率和其他重要的高速缓存存储器设计参数(例如未命中率和访问延迟)之间的权衡取舍,提供了有关HEVC编码器能耗的相关信息。第一项分析探讨了针对不同规格(例如容量,行大小)的缓存性能。结果表明,大部分能量都花在了读取操作上(一级缓存中将近73%),这表明HEVC编码器可以受益于低读取能量成本的存储技术。该分析还指出,增加容量对一级缓存的能源性能的影响更大,与一级缓存相比,平均能耗高34.78%。基于此调查,我们报告了每种视频分辨率最适合HEVC编码器的缓存规范。第二个分析讨论了HEVC输入参数对高速缓存性能的影响,表明BD-BR可以节省多达30%的能量,而将BD-BR的能耗增加2%。提出了HM(HEVC模型)和x265(H.265视频编解码器)HEVC软件模型之间的比较分析,表明x265更快(加速至648x),并且具有更高的缓存效率,提供了更少的内存能量(平均31.38%)。 HM实施。通过提出的框架获得的结果表明,视频编码参数的管理与应用程序调整的缓存规范相结合,具有在保持视频质量的同时降低视频编码系统能耗的巨大潜力。

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