A graphite based STT-RAM cell with reduction in switching current

摘要

Spin Transfer Torque Random Access Memory (STT-RAM) is a serious candidate for "universal memory" because of its non-volatility, fast access time, high density, good scalability, high endurance and relatively low power dissipation. However, problems with low write speed and large write current are important existing challenges in STT-RAM design and there is a tradeoff between them and data retention time. In this study, a novel STT-RAM cell structure which uses perfect graphite based Magnetic Tunnel Junction (MTJ) is proposed. First, the cross-section of the structure is selected to be an ellipse of 45 nm and 180 nm dimensions and a six-layer graphite is used as tunnel barrier. By passing a lateral current with a short pulse width (before applying STT current and independent of it) through four middle graphene layers of the tunnel barrier, a 27% reduction in the amplitude of the switching current (for fast switching time of 2 ns) or a 58% reduction in its pulse width is achieved without any reduction in data retention time. Finally, the effect of downscaling of technology on the proposed structure is evaluated. A reduction of 31.6% and 9% in switching current is achieved for 90 and 22 nm cell width respectively by passing sufficient current (100 μA with 0.1 ns pulse width) through the tunnel barrier. Simulations are done using Object Oriented Micro Magnetic Framework (OOMMF).