Implementations of smart pixels for optoelectronic processors and interconnection systems. II. SEED-based technology and comparison with optoelectronic gates

摘要

For part I see ibid., vol. 11, no. 10, pp. 1659-1669 (Oct. 1993). In part I, the authors discussed the optoelectronic approach to the implementation of smart pixels for optical interconnection and optical computing systems. In this second paper, a similar analysis is done for SEED-based technologies. The technologies investigated include the symmetric SEED (S-SEED), asymmetric Fabry-Perot (ASFP) SEED, shallow quantum well SEED, and FET-SEED. Of these technologies, it is found that FET-SEED (whose structure is closely similar to optoelectronic logic gates) has the highest sensitivity and operates at the highest bandwidth. The advantages and limitations of the two approaches are compared, considering such system performance issues as the maximum information flux density, temperature sensitivity, and optical coupling efficiency. It is concluded that the optoelectronic approach is useful in applications which require high bandwidth (<1 GHz), complex logic functions, and moderate pixel density, while the SEED-based approach is more suitable to high-density interconnections used at moderate bandwidths (>100 MHz). Furthermore, the maximum information flux density of 2-D optoelectronic and FET-SEED logic gates is approximately 200 GHz/cm/sup 2/, which is from 1 to 2 orders of magnitude larger than for other SEED-based array technologies.