Design Of Low Power Double Edge Triggered Flip Flop

摘要

A double edge triggered flip flop latches data at both edges of clock and hence it is advantageous over single edge-triggered flip flop in terms of power consumption and operating speed. Design of a low power double edge triggered D flip flop (DETFF) has been presented in this paper and it has been compared with three previously published DETFFs for their performances and power consumption. The DETFF circuits were simulated using TSPICE for 0.13 m technology CMOS process for different operating frequencies and supply voltages. The proposed design is shown to have the lowest power delay product (PDF) with respect to other double edge triggered flip-flops in all the above conditions.