A double edge triggered flip flop latches data at both edges of clock and hence it is advantageous over single edge-triggered flip flop in terms of power consumption and operating speed. Design of a low power Double Edge Triggered D Flip Flop (DETDFF ) has been presented in this study and it is compared with two previously published DETDFFs for their performance and power consumption. The DETDFF circuits were simulated using TSPICE for 0.13 and 0.18μ technology CMOS process for different supply voltages. The proposed design is shown to have the lowest power consumption with respect to other double edge triggered flip-flops in all the above conditions.
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