Memory Power Optimization on Different Memory Address Mapping Schemas

摘要

Memory accounts for a large and increasing fraction of the energy consumed by computers. To save energy, memory manufacturers design memory devices in different power/work modes. Hardware and software power controls have been proposed to take full advantage of these different modes. In this paper, we analyze the effects of different memory address mapping schemas on power mode control. Note that a memory address mapping schema translates a given physical address to a specific memory cell in DRAM system. We find that most of existing power mode controls are sensitive to memory address mapping schemas that can be categorized as high-bit multi-access cross memory (HMCM) and low-bit multi-access cross memory (LMCM). For the former schema, we propose a rank-sensitive buddy system (RS-Buddy) to cluster pages together to prolong memory modules' time in low power mode. For the latter schema, we introduce a comprehensive solution named MSPA. It adopts a memory address segmentation module to split memory into many regions, configured as different mapping schemas. With the help of an OS power-aware memory allocator, MSPA dynamically allocates one application's memory from its preferred region to balance power and performance. Extensive experiments on practical platform for HMCM show that RS-Buddy can adapt to finer-grained schemas and effectively optimize memory power efficiency. Furthermore, our simulation results of LMCM demonstrate that MSPA can further improve the power efficiency by 3% to 17% when combined with previous arts.