Hardware Prototyping for Various Transforms in H.264 High Profile

摘要

In H.264/AVC, the concept of adapting the transform size to the block size of prediction residue has proven to be an important coding tool. This paper presents a high-throughput, cost-effective implementation for the various types of integer transforms supported in the H.264 high profile coders. First, a pipelined structure for integer 4x4 DCT (Discrete cosine transform) and 8x8 DCT with high utilization is proposed, in which only one 1-D 4×1 or 8×1 transform unit and one 4x4 or 8x8 register array are used, 4x4 and 8x8 DCT can be processsed in 5 cycles and 21 cycles respectively. Second, the structure for 2-level hierarchical transforms based on 4x4 DCT and 4x4 HDT (Hadamard transform) is also proposed, an multi transform structure which can process 4x4 DCT or HTD adaptively is used. This architecture processes all calculations of 4x4 DCT and 4×4 HDT in an unified architecture. Sixteen 4x4 residue blocks and one 4×4 DC block are in pipelining processing, and can be implemented within 21 cycles. The designs are implemented with 0.13 /mi CMOS technology, experimental results show that the proposed architectures achieve high performance and can satisfy Quad Full High Definition (QFHD) (3840×2160@30fps) coding while trading off high performance and low power against chip area.