An Effective Modeling of Power Consumption and Time Delay for SRAM Compiler

摘要

This paper presents an effective power consumption modeling, as well as access time delay modeling, which aim to get the expenditure of power and time for various SRAM IP generated by SRAM compiler without complicated calculation and specific circuit analysis during operation. According to a segment analysis based on various MUX, bivariate power model on basis of two-dimensional bilinear interpolation function is proposed. By dividing the delay time into several parts (mainly, decoder delay, word line delay, bit line delay, and SA delay), critical path time delay network model is presented. Simulation results by HSIM in SMIC 65 nm CMOS technology show that the average inaccuracy is about 5%.