Modelling and optimization of CMOS winner-takes-all circuit for improved slew rate using swarm intelligence based techniques

摘要

In emulating biological behavior of vertebrates, neuromorphic integrated chips are being widely employed. CMOS Winner-Takes-All (WTA) circuit is one of the key component of neuromorphic integrated chips. The modelling of the WTA circuit has been carried out and few modern Evolutionary Optimization algorithms have also been employed to optimize the circuit parameters in order to improve slew rate. Simulations for optimization were performed using MATLAB. The results found are compared with each other. Based on the optimized results, circuit is designed in Cadence Virtuoso and simulated in Cadence Spectre from which the optimum resolution is also obtained and results are validated.