Current Consumption and Power Integrity of CMOS Digital Circuits Under NBTI Wearout

摘要

In this paper the power consumption and power integrity of a CMOS ring oscillator has been analysed when their pFETs are subjected to negative bias temperature instability (NBTI). The impact of pFET under NBTI has been experimentally quantified whereas CMOS ring oscillator power consumption and power integrity have been evaluated by means of electrical full-model simulation. The results show that power consumption is reduced and power integrity remains constant with NBTI wearout..