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首页> 外文期刊>Journal of Electronic Packaging >From Chip to Cooling Tower Data Center Modeling: Chip Leakage Power and Its Impact on Cooling Infrastructure Energy Efficiency
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From Chip to Cooling Tower Data Center Modeling: Chip Leakage Power and Its Impact on Cooling Infrastructure Energy Efficiency

机译:从芯片到冷却塔数据中心建模:芯片泄漏功率及其对冷却基础设施能源效率的影响

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摘要

The power consumption of the chip package is known to vary with operating temperature, independently of the workload processing power. This variation is commonly known as chip leakage power, typically accounting for ~10% of total chip power consumption. The influence of operating temperature on leakage power consumption is a major concern for the information technology (IT) industry for design optimization where IT system power densities are steadily increasing and leakage power expected to account for up to ~50% of chip power in the near future associated with the reducing package size. Much attention has been placed on developing models of the chip leakage power as a function of package temperature, ranging from simple linear models to complex super-linear models. This knowledge is crucial for IT system designers to improve chip level energy efficiency and minimize heat dissipation. However, this work has been focused on the component level with little thought given to the impact of chip leakage power on entire data center efficiency. Studies on data center power consumption quote IT system heat dissipation as a constant value without accounting for the variance of chip power with operating temperature due to leakage power. Previous modeling techniques have also omitted this temperature dependent relationship. In this paper, we discuss the need for chip leakage power to be included in the analysis of holistic data center performance. A chip leakage power model is defined and its implementation into an existing multiscale data center energy model is discussed. Parametric studies are conducted over a range of system and environment operating conditions to evaluate the impact of varying degrees of chip leakage power. Possible strategies for mitigating the impact of leakage power are also illustrated in this study. This work illustrates that when including chip leakage power in the data center model, a compromise exists between increasing operating temperatures to improve cooling infrastructure efficiency and the increase in heat load at higher operating temperatures due to leakage power.
机译:已知芯片封装的功耗随工作温度而变化,与工作负载处理能力无关。这种变化通常称为芯片泄漏功率,通常占芯片总功耗的约10%。工作温度对泄漏功耗的影响是信息技术(IT)行业进行设计优化的主要关注点,在该行业中,IT系统的功率密度正在稳步提高,并且泄漏功率预计将占芯片功率的近50%。未来与减小包装尺寸有关。从简单的线性模型到复杂的超线性模型,开发基于芯片封装温度的芯片泄漏功率模型已经引起了人们的广泛关注。这些知识对于IT系统设计人员提高芯片级能效并最小化散热至关重要。但是,这项工作一直集中在组件级别,很少考虑芯片泄漏功率对整个数据中心效率的影响。关于数据中心功耗的研究将IT系统的散热量作为一个恒定值,而不考虑芯片功耗随泄漏功耗而变化的工作温度的变化。先前的建模技术还省略了这种温度相关关系。在本文中,我们讨论了在整体数据中心性能分析中包括芯片泄漏功率的需求。定义了芯片泄漏功率模型,并讨论了其在现有多尺度数据中心能量模型中的实现。在一系列系统和环境操作条件下进行了参数研究,以评估不同程度的芯片泄漏功率的影响。这项研究还说明了减轻泄漏功率影响的可能策略。这项工作表明,在数据中心模型中包括芯片泄漏功率时,在增加工作温度以提高冷却基础设施效率和在更高工作温度下由于泄漏功率而增加热负荷之间存在折衷。

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  • 来源
    《Journal of Electronic Packaging》 |2012年第4期|041009.1-041009.8|共8页
  • 作者单位

    Stokes Institute, University of Limerick, Limerick, Ireland;

    Stokes Institute, University of Limerick, Limerick, Ireland;

    Stokes Institute, University of Limerick, Limerick, Ireland;

    Hewlett-Packard Laboratories, Palo Alto, CA 94304;

    Hewlett-Packard Laboratories, Palo Alto, CA 94304;

    Hewlett-Packard Laboratories, Palo Alto, CA 94304;

    HP Enterprise Business, Liberty Lake, WA 99019;

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