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A Simple Harmonic Reduction Method in 20-Pulse AC-DC Converter

机译:20脉冲AC-DC转换器中的一种简单的谐波降低方法

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This paper proposes a simple and passive harmonic reduction method at dc link of 20-pulse rectifier. The 20-pulse topology is obtained via two paralleled 10-pulse ac-dc converters, each of them consisting of a five-phase (five-leg) diode bridge rectifier. For independent operation of the paralleled diode-bridge rectifiers, a zero sequence blocking transformer (ZSBT) is designed and implemented. Connection of a tapped inter-phase transformer (IPT) at the output of the ZSBT results in doubling the number of the output voltage pulses. The application of the pulse doubling technique with a low power rating (2% of the load power rating) results in a simpler and more economical con figuration of the whole system and increased number of pulses. The design is suitable for retro fit applications where a six-pulse diode bridge rectifier is being utilized. The proposed structure is simulated using Matlab/Simulink software under different loading conditions. The simulation results con firm the significant improvement of the power quality indices (IEEE-519 standard requirements) at the point of common coupling (PCC). Experimental results are obtained using the designed and constructed laboratory prototype of the proposed converter to validate the design procedure and the simulation results. The VA rating of the magnetic circuit is calculated to con firm the savings in space, volume, weight and cost of the proposed configuration.
机译:本文提出了一种20脉冲整流器直流环节的简单而无源的谐波降低方法。 20脉冲拓扑是通过两个并联的10脉冲AC-DC转换器获得的,每个转换器都由一个五相(五脚)二极管桥式整流器组成。为了使并联的二极管桥式整流器独立运行,设计并实现了零序阻塞变压器(ZSBT)。在ZSBT的输出端连接一个带抽头的相间变压器(IPT)会使输出电压脉冲的数量增加一倍。具有低额定功率(负载额定功率的2%)的脉冲加倍技术的应用导致整个系统的配置更加简单和经济,并增加了脉冲数。该设计适用于采用六脉冲二极管桥式整流器的翻新应用。在不同的加载条件下,使用Matlab / Simulink软件对拟议的结构进行了仿真。仿真结果确保了在公共耦合点(PCC)处电能质量指标(IEEE-519标准要求)的显着改善。实验结果是使用拟议的转换器的设计和建造的实验室原型获得的,以验证设计程序和仿真结果。计算磁路的VA额定值可以确保节省空间,体积,重量和所建议配置的成本。

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