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Vertical power MOS transistor as a thermoelectric quasi-nanowire device

机译:垂直功率MOS晶体管作为热电准纳米线器件

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摘要

Nano-materials exhibit superior performance over bulk materials in a variety of applications such as direct heat to electricity thermoelectric generators (TEGs) and many more. However, a gap still exists for the integration of these nano-materials into practical applications. This study explores the feasibility of utilizing the advantages of nano-materials' thermo-electric properties, using regular bulk technology. Present-day TEGs are often applied by dedicated thermoelectric materials such as semiconductor alloys (e.g., PbTe, BiTe) whereas the standard semiconductor materials such as the doped silicon have not been widely addressed, with limited exceptions of nanowires. This study attempts to close the gap between the nano-materials' properties and the well-established bulk devices, approached for the first time by exploiting the nano-metric dimensions of the conductive channel in metal-oxide-semiconductor (MOS) structures. A significantly higher electrical current than expected from a bulk silicon device has been experimentally measured as a result of the application of a positive gate voltage and a temperature gradient between the "source" and the "drain" terminals of a commercial NMOS transistor. This finding implies on a "quasi-nanowire" behaviour of the transistor channel, which can be easily controlled by the transistor's gate voltage that is applied. This phenomenon enables a considerable improvement of silicon based TEGs, fabricated by traditional silicon technology. Four times higher ZT values (TEG quality factor) compared to conventional bulk silicon have been observed for an off-the-shelf silicon device. By optimizing the device, it is believed that even higher ZT values can be achieved..
机译:在各种应用中,例如直接热电热电发电机(TEG)等,纳米材料表现出比块状材料优越的性能。然而,将这些纳米材料集成到实际应用中仍然存在差距。这项研究探索了使用常规本体技术利用纳米材料的热电特性优势的可行性。当前的TEG通常由专用的热电材料例如半导体合金(例如,PbTe,BiTe)施加,而标准的半导体材料例如掺杂的硅尚未得到广泛解决,除了纳米线的有限例外。这项研究试图通过利用金属氧化物半导体(MOS)结构中的导电通道的纳米尺寸,来缩小纳米材料的性能与成熟的大体积器件之间的差距。由于在商用NMOS晶体管的“源极”和“漏极”端子之间施加了正的栅极电压和温度梯度,因此已经通过实验测量了比体硅器件预期的电流高得多的电流。这一发现暗示着晶体管通道的“准纳米线”行为,可以通过施加的晶体管的栅极电压轻松地对其进行控制。这种现象可以大大改善通过传统硅技术制造的硅基TEG。对于现成的硅器件,已观察到的ZT值(TEG品质因数)是传统体硅的四倍。通过优化设备,相信可以实现更高的ZT值。

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  • 来源
    《Journal of Applied Physics》 |2016年第24期|244903.1-244903.5|共5页
  • 作者单位

    Unit of Energy Engineering, Ben-Gurion University of the Negev, Beer-Sheva 84105, Israel;

    Department of Materials Engineering, Nuclear Research Center Negev, P.O. Box 9001, Beer-Sheva, Israel;

    The Center for Power Electronics and Mixed-Signal IC, Department of Electrical and Computer Engineering,Ben-Gurion University of the Negev, Beer-Sheva 84105, Israel;

    Unit of Energy Engineering, Ben-Gurion University of the Negev, Beer-Sheva 84105, Israel,Department of Materials Engineering, Ben-Gurion University of the Negev, Beer-Sheva 84105, Israel;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
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  • 正文语种 eng
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