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首页> 外文期刊>Japanese journal of applied physics >1.2 kV silicon carbide Schottky barrier diode embedded MOSFETs with extension structure and titanium-based single contact
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1.2 kV silicon carbide Schottky barrier diode embedded MOSFETs with extension structure and titanium-based single contact

机译:1.2 kV碳化硅肖特基势垒二极管嵌入式MOSFET,延长结构和基于钛的单触点

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摘要

Recently, to avoid forward-voltage degradation of body diodes, which is caused by the expansion of stacking faults due to hole-current conduction through the body diodes, silicon carbide (SiC) Schottky barrier diode (SBD) embedded metal-oxide-semiconductor field effect transistors have been actively studied. However, most studies focus on designs that do not allow hole current to flow when reverse current flows from the source to drain, and there are few reports that mention the contact-formation process or contact reliability. A low-resistance ohmic contact and a highly reliable Schottky contact were formed simultaneously by combining the recrystallization of an N+ heavily implanted region to 3C-SiC, opening of a contact hole by dry etching and formation of a titanium electrode followed by post-annealing. Moreover, gate leakage current can be reduced by improving the crystallinity and morphology near the channel by introducing an extension structure, even if the process for simultaneously forming the ohmic and Schottky contacts is applied to the MOSFETs fabrication process. The developed process minimizes the increase in cell pitch due to the incorporation of the SBD and suppresses the conventional increase in on-resistance to about 10%. Regarding diode characteristics, expansion of the stacking faults could be suppressed by eliminating the hole-current conduction, even in the case of a large current density of 500 A cm(-2) at 175 degrees C. (C) 2020 The Japan Society of Applied Physics
机译:最近,为了避免身体二极管的前向电压劣化,这是由于通过通过体二极管,碳化硅(SiC)肖特基势垒二极管(SBD)嵌入金属氧化物半导体场而引起的堆叠故障引起的堆叠故障引起的已经主动研究了效果晶体管。然而,大多数研究专注于设计的设计,当反向电流从源流出时不允许孔电流流动,并且很少有报告提及接触形成过程或接触可靠性。通过将N +重植入区域的重结晶与3C-SiC的重结晶,通过干蚀刻和形成钛电极,然后进行后退火,同时形成低电阻欧姆接触和高度可靠的肖特基触点。此外,即使将用于同时形成欧姆和肖特基触点的过程应用于MOSFET制造工艺,也可以通过在延伸结构改善通道附近的结晶度和形态来降低栅极泄漏电流。由于SBD的掺入,开发过程最小化了细胞间距的增加,并抑制了常规增加的导通耐受约10%。关于二极管特性,即使在175摄氏度为500℃(C)2020的大电流密度为500a cm(-2)的情况下,也可以通过消除空穴电流传导来抑制堆叠故障的膨胀。(c)2020日本社会应用物理学

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  • 来源
    《Japanese journal of applied physics》 |2020年第2期|026502.1-026502.7|共7页
  • 作者单位

    Hitachi Ltd Res & Dev Grp Ctr Technol Innovat Elect Kokubunji Tokyo 1878601 Japan|Univ Tsukuba Grad Sch Pure & Appl Sci Tsukuba Ibaraki 3058573 Japan;

    Hitachi Ltd Res & Dev Grp Ctr Technol Innovat Elect Kokubunji Tokyo 1878601 Japan;

    Hitachi Ltd Res & Dev Grp Ctr Technol Innovat Elect Kokubunji Tokyo 1878601 Japan;

    Hitachi Ltd Res & Dev Grp Ctr Technol Innovat Elect Kokubunji Tokyo 1878601 Japan;

    Univ Tsukuba Grad Sch Pure & Appl Sci Tsukuba Ibaraki 3058573 Japan;

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