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首页> 外文期刊>Japanese journal of applied physics >Novel Ni silicide formed with a Ni/Er/Ni/TiN structure for thermal stable and low contact resistance source/drain in MOSFETs
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Novel Ni silicide formed with a Ni/Er/Ni/TiN structure for thermal stable and low contact resistance source/drain in MOSFETs

机译:具有Ni / Er / Ni / TiN结构的新型Ni硅化物可实现MOSFET中的热稳定和低接触电阻源/漏

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摘要

In this paper, Ni silicide formed with a Ni/Er/Ni/TiN structure is proposed, and the thermal stability and electrical properties of the proposed Ni silicide with an Er interlayer in different positions are studied for application to source/drain of MOSFETs. Ni silicide with Ni/Er/Ni/TiN structures showed not only improved thermal stability but also lower sheet resistance than an Er/Ni/TiN structure. Moreover, proposed Ni/Er/Ni/TiN (2/2/ 11/10nm) structure exhibited great barrier height and low ideality factor similar to the Er/Ni/TiN structure which could reduce the contact resistance between silicide and doped source/drain region. Therefore, proposed silicide using Ni/Er/Ni/TiN (2/2/11/10nm) structure is promising for MOSFET source/drain due to better thermal stability, low sheet resistance, and excellent electrical properties.
机译:本文提出了一种具有Ni / Er / Ni / TiN结构的硅化镍,并研究了其在不同位置具有Er中间层的硅化镍的热稳定性和电学性质,以用于MOSFET的源/漏。与Er / Ni / TiN结构相比,具有Ni / Er / Ni / TiN结构的硅化镍不仅显示出改善的热稳定性,而且还显示出较低的薄层电阻。此外,拟议的Ni / Er / Ni / TiN(2/2/11 / 10nm)结构与Er / Ni / TiN结构相似,具有较高的势垒高度和较低的理想因子,可以降低硅化物与掺杂源极/漏极之间的接触电阻区域。因此,建议的使用Ni / Er / Ni / TiN(2/2/11 / 10nm)结构的硅化物由于具有更好的热稳定性,较低的薄层电阻和出色的电性能,因此有望用于MOSFET的源极/漏极。

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  • 来源
    《Japanese journal of applied physics》 |2014年第8s3期|08NE05.1-08NE05.5|共5页
  • 作者单位

    Department of Electronics Engineering, Chungnam National University, Daejeon 305-764, Korea;

    Department of Electronics Engineering, Chungnam National University, Daejeon 305-764, Korea;

    Department of Electronics Engineering, Chungnam National University, Daejeon 305-764, Korea;

    Department of Electronics Engineering, Chungnam National University, Daejeon 305-764, Korea;

    Department of Electronics Engineering, Chungnam National University, Daejeon 305-764, Korea;

    Department of Electronics Engineering, Chungnam National University, Daejeon 305-764, Korea;

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