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首页> 外文期刊>Japanese journal of applied physics >Analysis of breakdown voltage of area surrounded by multiple trench gaps in 4 kV monolithic isolator for communication network interface
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Analysis of breakdown voltage of area surrounded by multiple trench gaps in 4 kV monolithic isolator for communication network interface

机译:通信网络接口的4 kV单片隔离器中被多个沟槽间隙包围的区域的击穿电压分析

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摘要

We analyzed the shared voltages of multiple trench gaps on a silicon-on-insulator (SOI) substrate and showed the conditions for improving the breakdown voltage surrounded by these isolated structures. We introduced a unified impedance model instead of the capacitive model of trench gaps and determined the effective conditions for improving the breakdown voltage. The first condition is to reduce the impedance of trench gaps. In this case, the leak current gives a low limit of trench gap resistance. The second condition is to increase the substrate resistance. As silicon substrate resistance is not very high, this condition is not useful for the silicon substrate, but for other materials such as ceramics. We confirmed the effectiveness of these conditions from the simulation and experimental results of a fabricated chip. (C) 2015 The Japan Society of Applied Physics
机译:我们分析了绝缘体上硅(SOI)衬底上多个沟槽间隙的共享电压,并显示了改善这些隔离结构所包围的击穿电压的条件。我们引入了统一的阻抗模型,而不是沟槽间隙的电容模型,并确定了改善击穿电压的有效条件。第一个条件是降低沟槽间隙的阻抗。在这种情况下,泄漏电流给出了沟槽间隙电阻的下限。第二个条件是增加衬底电阻。由于硅衬底的电阻不是很高,因此该条件对硅衬底无用,但对其他材料(如陶瓷)无用。我们从制造的芯片的仿真和实验结果证实了这些条件的有效性。 (C)2015年日本应用物理学会

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