Automatic identification number generation circuit using nmos pair current mismatch

摘要

This paper presents a uniquely distributed identification number generation circuit based on process variation. The developed circuit utilizes current mismatch in an NMOS pair for unique ID output. To evaluate the output 1/0 probability-uniformity and process dependence, we fabricated a prototype in two different 0.18-mu m standard CMOS technologies. We tested 382 chips and calculated the hamming distances between each chip. The results show the hamming distance distribution agrees with theoretical binominal distribution in mean and skewness. However, the distribution is a little wider than the theoretical one. We investigated the reason for the difference and found that circuit layout irregularity causes degradation in standard deviation and kurtosis. When the bits at both ends are excluded, the ID outputs agree with theoretical statistics. The results show the circuit architecture generates a unique and process-independent ID. (C) 2015 The Japan Society of Applied Physics