In recent years, 3-D integrated circuits in which active layers are stacked have been re- searched. In order to design large scale 3-D integrated circuits, layout automation is indis- pensable, but placement method in the layout design has not been researched yet. This paper proposes a placement method for 3-D VLSI based on estimated positions. In the method, an estimated position of each cell is calculated such that the estimated wire length is reduced. Then adjacent cells are interchanged to improve the sum of difference between cell positions and their estimated positions. The experimental results are also shown.
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