Proposing an Efficient Method to Estimate and Reduce Crosstalk after Placement in VLSI Circuits

摘要

Due to the increasing number of elements on a single chip area and the growing complexity of routing, existing methods to reduce crosstalk at the routing or post-routing stage do not seem efficient anymore. So crosstalk estimation should be considered in earlier design stages such as placement. To estimate crosstalk after placement information about the topology of a net and adjacency of its wire-segments should be available. Yet it is not because of the lack of routing information. In this paper, we propose a probabilistic method to estimate intra-grid wirelength of nets after placement and global routing. Results of incorporating this method with the previous crosstalk estimation schemes and our proposed crosstalk reduction method show its efficiency in detecting failing noisy nets before having detailed information of wire adjacency. Our general method improved the number of correctly detected failing noisy nets by 15% on average. In a second improvement, the directed version of this method increased the number of correct detections by 19%. It also decreased the number of false detections considerably.