Systolic traffic modelling in network on chip

摘要

In this paper, we present the systolic architecture unit in NoC and address the fundamental issue of traffic modelling for systolic architectures unit in SoC design. We improve the synthetic trace generation method in order to simulate in systolic architectures unit and analyse the effect of the systolic architecture for traffic model, give the function H_Y=F(H_(X1),H_(X2)) by simulating and surface fitting for 2-input and 1-output systolic architecture unit traffic model. Our proposed technique allows designers implementing on-chip communication networks to model the traffic of any application by systolic architectures unit more effectively. This will enable systems designers to optimally their mapping and routing, architectures, and so on. Ultimately, designers will achieve optimal trade-off performance metrics and application quality.