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首页> 外文期刊>International journal of unconventional computing >Volistor Logic Gates in Crossbar Arrays of Rectifying Memristors
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Volistor Logic Gates in Crossbar Arrays of Rectifying Memristors

机译:整流忆阻器的交叉开关阵列中的压敏逻辑门

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摘要

This paper introduces new implementations for volistors (voltage-resistor gates) and programmable mDiode (memristive Diode) gates in crossbar arrays of rectifying memristors. Volistors use voltage as input and resistance as output and rely on the diode behavior of rectifying memristors. The design constraints of volistors are explained. These constraints determine the size of the crossbar arrays and the voltage levels for logic functions implementations. This paper shows how volistors can be cascaded in crossbar arrays with other memristive gates such as programmable mDiode gates. An implementation example of AND-NOR PLA (Programmable Logic Array) based on hybrid programmable mDiode gates and volistors in crossbar arrays is described. This PLA circuit reduces both size and delay when compared to other memristive PLAs (mPLAs) realized with stateful gates, CRS (complementary resistive switches) based gates, and Boolean gates. The outcomes show the benefit of the new memristive circuits approaches.
机译:本文介绍了在整流忆阻器的交叉开关阵列中的压敏电阻(电压门)和可编程mDiode(忆阻二极管)门的新实现。压敏电阻将电压用作输入,将电阻用作输出,并依赖于整流忆阻器的二极管性能。解释了压敏电阻的设计约束。这些约束条件确定了交叉开关阵列的大小以及逻辑功能实现的电压电平。本文展示了如何将压敏电阻与其他忆阻门(例如可编程mDiode栅极)层叠在交叉开关阵列中。描述了基于交叉开关阵列中的混合可编程mDiode栅极和压敏电阻的AND-NOR PLA(可编程逻辑阵列)的实现示例。与使用状态门,基于CRS(互补电阻开关)的门和布尔门实现的其他忆阻PLA(mPLA)相比,此PLA电路减少了尺寸,并减少了延迟。结果表明了新型忆阻电路方法的好处。

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