Design and analysis of variable attenuator with simultaneous minimized flat amplitude error and insertion phase variations

摘要

This paper presents a design of an analog variable attenuator with simultaneousminimized flat amplitude error and insertion phase variation over awide bandwidth and high attenuation range. The parasitic of PIN is compensatedwith series transmission lines loaded and shunt capacitors to achieveminimum flat amplitude error and insertion phase variation. Mechanism forsimultaneous reduction in flat amplitude error and phase variations isobtained by developing an analytical design equation using the PIN diodeequivalent circuit model. For the experimental validation, two kinds of proposedattenuators are designed and measured over 1 GHz bandwidth at a centerfrequency (f_0) of 3.5 GHz. The measurement results are consistent with thesimulation results. From the experiments, design-I provides an attenuationvariation of 0.9 dB to 20 dB with a maximum flat amplitude error of 0.65 dBand insertion phase variation of 5.70° over 1 GHz bandwidth. Similarly, thedesign-II provides an attenuation variation of 1.06 dB to 20 dB with a maximumamplitude error of 0.49 dB and insertion phase variation of 3.19° overthe same 1 GHz bandwidth.