Dynamic control of the batch processor in a serial-batch processor system with mean tardiness performance

摘要

Effective control of batch processors is very essential to improve on-time delivery of wafers in semiconductor manufacturing. In this paper, the focus is on mean tardiness performance of a batch processor in a two-stage processor system by including an upstream serial processor. Two new control strategies are proposed for this problem. The first strategy effectively incorporates the product information at the upstream serial station in batching decisions. The second strategy further applies a re-sequencing approach in the serial processor's queue when there is a benefit in shortening the arrival time of an urgent product. Discrete event simulation is used to test the performance of the strategies. Results are very promising as compared to benchmark control strategies.