Analog implementation of radix-2, 16-FFT processor for OFDM receivers: non-linearity behaviours and system performance analysis

摘要

Analog implementations of decoders have been widely studied by considering circuit complexity, as well as power and speed, and their integration with other analog blocks is an extension of analog decoding research. In the front-end blocks of orthogonal frequency-division multiplexing (OFDM) systems, combination of an analog fast Fourier transform (FFT) with an analog decoder is suitable. In this article, the implementation of a 16-symbol FFT processor based on analog complementary metal-oxide-semiconductor current mirrors within circuit and system levels is presented, and the FFT is implemented using a butterfly diagram, where each node is implemented using analog circuits. Implementation details include consideration of effects of transistor mismatch and inherent noises and effects of circuit non-linearity in OFDM system performance. It is shown that not only can transistor inherent noises be measured but also transistor mismatch can be applied as an input-referred noise source that can be used in system- and circuit-level studies. Simulations of a radix-2, 16-symbol FFT show that proposed circuits consume very low power, and impacts of noise, mismatch and non-linearity for each node of this processor are very small.