Analysis of 14nm technology node In_(0.53)Ga_(0.47)As nFinFET integrated with In_(0.53)Al_(0.48)As cap layer for high-speed circuits

摘要

CMOS (Complementary Metal-oxide-semiconductor) based high-speed applications in the sub-14 nm technology node using InGaAs Fin field-effect-transistors (FinFETs) confront with inevitable effect in form of interface traps upon integration of dielectric layer with InGaAs material. In this work, we have explored the impact of the traps on short channel effects (SCEs) and a technique of abating the effect of interface traps by introducing In(0.52)Al0.As-48 cap layer. Proposed work reforms the device by varying the cap layer thickness (Tcap), doping concentrations of cap layer and underlap region. The effect of traps on intrinsic delay, work function variation and SCEs was investigated to assess the trend on devices with In0.52Al0.48As cap layer. It has been observed that introduction of Tcap improves SCEs and helps to mitigate the effect of interface traps. SCEs can be additionally diminished by presenting underlap fin length at the cost of higher delay. The experimental results show the value of subthreshold swing = 149.54 mV/decade, drain-induced barrier lowering = 38.5 mV V-1 and delay = 1.1 ps for T-cap = 4 nm without underlap fin length structure for traps concentration of 10(12) cm(-2)eV(-1). Thus, significant improvement has been seen in SCEs and delay performance in FinFET structure with cap layer.