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Synthesis and Implementation of Reconfigurable PLC on FPGA Platform

机译:FPGA平台上可重构PLC的综合与实现

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The paper presents a set of algorithms dedicated for synthesis of reconfigurable logic controllers implemented on FPGA platform and programmed according to IEC1131 and EN61131. The program is compiled to hardware structure with a massive parallel processing. The developed method automatically allocates resources and operations. It controls resource usage and operation timing. Using mixed concept of operation allocation that considers operation timing and forms combinatorial chains of operations number of execution cycles can be reduced. An example of logic functions, PID controller and mixed arithmetic and logic programming examples are considered. Introducing the automatic implementation method allows flexible implementing the control algorithms. The maximal possible parallelism (limited only by the algorithm dependencies and available resources) is introduced.
机译:本文提出了一组专用于在FPGA平台上实现并根据IEC1131和EN61131进行编程的可重构逻辑控制器的合成算法。该程序被编译为具有大量并行处理的硬件结构。开发的方法自动分配资源和操作。它控制资源使用和操作时间。使用考虑了操作时序并形成操作组合链的混合操作分配概念,可以减少执行周期的数量。考虑逻辑功能示例,PID控制器以及混合算术和逻辑编程示例。引入自动实现方法可以灵活地实现控制算法。引入了最大可能的并行性(仅受算法依赖性和可用资源限制)。

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