Synthesis of an Application Specific Instruction Set Processor (ASIP) for RIPEMD-160 Hash Algorithm

摘要

Hash functions are vital tasks in many applications such as digital fingerprinting, Internet communications, bank transactions and so forth. RACE Integrity Primitives Evaluation Message Digest-160 (RIPEMD-160) is one of the most applicable hash functions that there have been several structures for designing it based on Application-Specific Integrated Circuit (ASIC) approach in the literature. Application-Specific Instruction Set Processor (ASIP) design makes compromise between ASIC and Digital Signal Processing approaches with respect to speed, cost and flexibility. Because of this unique property of ASIP method, an ASIP processor for RIPEMD-160 hash algorithm is presented in this article for the first time. A special Register Configuration (RC) for RIPEMD-160 hash algorithm is developed which its Instruction Set Architecture (ISA) includes 12 specific and 35 general instructions. Proposed ASIP is simulated with VHDL language in the behavioural level of abstraction, and a typical assembly code is written to show how the proposed ASIP performs hash function. Moreover, implementation results on Virtex5 Field Programmable Gate Array (FPGA) platform shows the superiority of the proposed processor in terms of performance against its counterparts.