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首页> 外文期刊>International Journal of Electronics Letters >A negative gyrator-C for purification of inductors in a differential LC-VCO
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A negative gyrator-C for purification of inductors in a differential LC-VCO

机译:负回转器-C,用于纯化差动LC-VCO中的电感器

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摘要

Based on the proposed technique, the negative resistor in a differential LC-VCO is configured to impose a negative gyrator-C across the output. This resolves the need for the inductive source degeneration already used for purification of inductors in a differential LC-VCO. In comparison, while the chip area is almost halved, phase noise at 100 kHz offset is noticeably improved from -95.7 to -100 dBc/Hz at no extra power consumption cost. Moreover, in the curve of phase noise versus frequency an inflection point shows up at the minimal. This feature prevents the conventional sharp degradation of the phase noise while the frequency is tuned and extends its minimum for hundreds of MHz to improve the reliability of design. The application of the proposed technique in design of a low power and low phase noise Giga Hertz-range CMOS differential LC-VCO around 2.9 GHz is illustrated and analysed. Post-layout simulations using CMOS 0.18 μm TSMC RF design kit are used for evaluation and comparison. Using 1.8 Vdc supply, the obtained power consumption, output level and tuning range are 2.6 mW, 2.3 Vpp and 12.4%, respectively.
机译:基于提出的技术,差分LC-VCO中的负电阻配置为在输出两端施加一个负回转器C。这解决了对已经用于差分LC-VCO中的电感器净化的电感源退化的需求。相比之下,虽然芯片面积几乎减半,但100 kHz偏移时的相位噪声从-95.7显着提高到-100 dBc / Hz,而没有额外的功耗。此外,在相位噪声与频率的关系曲线中,拐点最小。此功能可防止在调谐频率时传统的相位噪声急剧下降,并将其最小值扩展至数百MHz,以提高设计的可靠性。阐述并分析了所提出的技术在2.9 GHz附近的低功耗和低相位噪声千兆赫兹范围CMOS差分LC-VCO设计中的应用。使用CMOS 0.18μmTSMC RF设计套件进行布局后仿真,用于评估和比较。使用1.8 Vdc电源,获得的功耗,输出电平和调整范围分别为2.6 mW,2.3 Vpp和12.4%。

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