An improved DIM interface algorithm for the MMC-HVDC power hardware- in-the-loop simulation system

摘要

Power hardware-in-the-loop (PHIL) simulation has become the crucial means of research on modular multilevel converter based high voltage direct current (MMC-HVDC) devices. To deal with the stability and accuracy problems caused by the power interface, an improved damping impedance method (DIM) interface algorithm is proposed by real-time impedance matching in this paper. The trapezoidal integration method is used to disperse the sub-module capacitance, and the turn-off resistance of power device is set to infinity to simplify the calculation process of MMC equivalent impedance, which can realize the efficient impedance matching for the DIM. Moreover, based on the voltage signal reconstructed by a dq coordinate transformation, a time delay compensation control method is proposed for the uncertain interface delay to improve the accuracy of the PHIL simulation. To verify the excellent stability and accuracy performance of the improved DIM, the characteristics of the reference system, DIM and ideal transformer model (ITM) interface systems are compared by digital simulation. The start-up strategy of a practical MMC-HVDC PHIL test platform is designed, and the effectiveness and feasibility of the proposed methods are verified by simulation experiments.