A DESIGN SPACE EXPLORATION ALGORITHM IN COMPILING WINDOW OPERATION ONTO RECONFIGURABLE HARDWARE

摘要

Window operations which are computationally intensive and data intensive are frequently used in image compression, pattern recognition and digital signal processing. Reconfigurable hardware boards provide a convenient and flexible solution to speed up these algorithms. In this paper, we design a three-level memory structure to realize inner-loop and outer-loop data reuse in window operations completely, and use shifted registers to make hardware design simpler. Then, we present a design space exploration algorithm to get a high-performance design without going through the time-consuming hardware design process for each different algorithm. By finding the three upper bounds according to area constraints, memory bandwidth constraints and on-chip memory constraints, the block structure of the design which can fully utilize the available resources on the board is determined.