Efficient Hardware Realization of Advanced Encryption Standard Algorithm using Virtex-5 FPGA

摘要

This paper presents an efficient hardware realization of Rijndael Advanced Encryption Standard (AES) cryptographic algorithm using state-of-the-art Field Programmable Gate Array (FPGA). The design is coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL). Timing simulation is performed to verify the functionality of the designed circuit. Performance evaluation is also done in terms of throughput and area. The design implemented on state-of-the-art Xilinx Virtex-5 (XC5VLX50FFG676-3) FPGA achieves a throughput of 4.34 Gbits/s using a total of 399 slices.