A New Reconfigurable Hardware Architecture for Cryptography Applications using AES by different Substitution box (S-Box) and Random Round Selection

摘要

This paper proposes a high performance AES architecture with MUX based substitution box (S-Box) and random round selection. The byte substitution is an important part of the Advanced Encryption Standard (AES) and it is implemented using Field Programmable Gate Array (FPGA). The objective of this paper is to present an efficient realization of S-Box using hardware description language (HDL). The novel implementation of proposed AES architecture is analyzed and compared with the existing AES implementations. This proposed architecture implementation shows high speed and low area. The design is coded and downloaded into Xilinx Virtex-2 2vl500ff896 FPGA. The results obtained shows that this architecture provides an improved performance about 20% and reduction of 38% device utilization.