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首页> 外文期刊>International journal of computational intelligence research >FPGA Design of Effective Detection Low Power Architecture for Recycled ICs
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FPGA Design of Effective Detection Low Power Architecture for Recycled ICs

机译:回收IC有效检测低功耗架构的FPGA设计

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摘要

The counterfeiting and exercise of integrated circuits (ICs) became major issues in recent years, probably impacting the security and dependability of electronic systems certain for military, financial, or various crucial applications. With identical utility and packaging, it might be terribly difficult To differentiate recycled ICs from unused ICs. In this project, two forms of on-chip light-weight sensors area unit planned to identify recycled ICs by measurement circuit usage time once utilized within the sector. Recycled ICs detection supported aging in ring oscillators (ROs-based) and Anti-Fuse (AF-based) unit of measurement the two techniques given throughout this paper. The planned methodology is supposed pattern verilog compound protein, simulated pattern Modelsim and synthesized pattern Xilinx code.
机译:近年来,伪造和使用集成电路(IC)成为主要问题,可能会影响某些军事,金融或各种关键应用的电子系统的安全性和可靠性。使用相同的用途和包装,可能很难区分回收的IC和未使用的IC。在该项目中,计划使用两种形式的片上轻量传感器区域单元,以通过一次在该部门内利用测量电路的使用时间来识别回收的IC。循环集成电路的检测支持环形振荡器(基于ROs)和反熔丝(基于AF)测量单元中的老化,这是本文通篇给出的两种技术。计划的方法是假设模式Verilog复合蛋白,模拟模式Modelsim和合成模式Xilinx代码。

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