Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption

摘要

Some techniques for low power operation in VLSI using the lowest possible supply voltage coupled with an architectural optimization have shown that we can save power even if we increase silicon area. In this paper we present a strategy to reduce power consumption in FPGAs based on pipeline architectures working with a low supply voltage.