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A low distortion CMOS continuous-time common-mode feedback circuit

机译:低失真CMOS连续时间共模反馈电路

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In high-gain fully differential operational amplifier (FD op-amp) design, the output common-mode (CM) voltage of the FD op-amp is quite sensitive to device properties and mismatch. It is, therefore, necessary to add an additional control circuit, referred to as the common-mode feedback (CMFB) circuit, to stabilize the output CM voltage at some specified voltage. In this paper, we present a high linear CMOS continuous-time CMFB circuit based on two differential pairs and the source degeneration using MOS transistors. Theoretical analysis and SPICE simulation results are provided to validate our proposed ideas. Finally, we present two design applications of the proposed configuration, one is the FD folded-cascode op-amp and the other is the Multiply-by-Two circuit which is the key component in the popular 1.5 bit/stage pipelined analog-to-digital converter. Comparison with conventional topologies shows that the new configuration has attractive characteristics concerning their implementation in high linear analog integrated circuits. Copyright © 2010 John Wiley & Sons, Ltd.
机译:在高增益全差分运算放大器(FD运算放大器)设计中,FD运算放大器的输出共模(CM)电压对器件特性和失配非常敏感。因此,有必要添加一个额外的控制电路,称为共模反馈(CMFB)电路,以将输出CM电压稳定在某个指定电压。在本文中,我们提出了一种基于两个差分对和使用MOS晶体管的源极退化的高线性CMOS连续时间CMFB电路。提供理论分析和SPICE仿真结果以验证我们提出的想法。最后,我们介绍了拟议配置的两种设计应用,一种是FD折叠共源共栅运算放大器,另一种是乘二乘电路,这是流行的1.5位/级流水线模数转换器的关键组件。数字转换器。与常规拓扑的比较表明,新配置在高线性模拟集成电路中的实现方面具有吸引人的特性。版权所有©2010 John Wiley&Sons,Ltd.

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