A low-power small-area 10-bit analog-to-digital converter for neural recording applications

摘要

In vivo neural recording systems require low power and small area, which are the most important parameters in such systems. This paper reports a new architecture for reducing the power dissipation and area, in analog-to-digital converters (ADCs). A time-based approach is used for the subtraction and amplification in conjunction with a current-mode algorithm and cyclical stage, which the conversion reuses a single stage for three times, to perform analog-to-digital conversion. Based on introduced structure, a 10-bit 100-kSample/s time-based cyclical ADC has been designed and simulated in a standard 90-nm Complementary Metal Oxide Semiconductor (CMOS) process. Design of the system-level architecture and the circuits was driven by stringent power constraints for small implantable devices. Simulation results show that the ADC achieves a peak signal-to-noise and distortion ratio (SNDR) of 59.6 dB, an effective number of bits (ENOB) of 9.6, a total harmonic distortion (THD) of —64dB, and a peak integral nonlinearity (INL) of 0.55, related to the least significant bit (LSB). The ADC active area occupies 280 urn x 250 um. The total power dissipation is 5uW per conversion stage and 20 uW from an 1.2-V supply for full-scale conversion.