首页> 外文期刊>International journal of circuit theory and applications >Suppressing derivatives of selected variables in Verilog-A
【24h】

Suppressing derivatives of selected variables in Verilog-A

机译:抑制Verilog-A中选定变量的导数

获取原文
获取原文并翻译 | 示例
       

摘要

A former scaling technique made it possible to eliminate the effect of the automatically generated derivatives at bipolar non-quasi-static (NQS) modeling in Verilog-A. An alternative technique is proposed here, which makes the derivatives of selected variables zero. The method was verified on the examples of bipolar NQS variants. The confirming results open a new perspective for increasing the flexibility of Verilog-A compact modeling along with the reduction of computational efforts.
机译:以前的缩放技术使消除在Verilog-A中的双极非准静态(NQS)建模时自动生成的导数的影响成为可能。这里提出了一种替代技术,该技术使选定变量的导数为零。该方法已在双极NQS变体实例中得到验证。证实性的结果为增加Verilog-A紧凑建模的灵活性以及减少计算量开辟了新的前景。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号