机译:具有忆阻性STDP突触的潜伏神经元模型的LIF的硬件设计
Univ Roma Tor Vergata, Dept Elect Engn, Via Politech 1, I-00133 Rome, Italy;
Univ Roma Tor Vergata, Dept Elect Engn, Via Politech 1, I-00133 Rome, Italy;
Univ Roma Tor Vergata, Dept Elect Engn, Via Politech 1, I-00133 Rome, Italy;
Univ Roma Tor Vergata, Dept Elect Engn, Via Politech 1, I-00133 Rome, Italy;
Univ Roma Tor Vergata, Dept Elect Engn, Via Politech 1, I-00133 Rome, Italy;
Univ Roma Tor Vergata, Dept Elect Engn, Via Politech 1, I-00133 Rome, Italy;
Univ Roma Tor Vergata, Dept Elect Engn, Via Politech 1, I-00133 Rome, Italy;
Univ Roma Tor Vergata, Dept Elect Engn, Via Politech 1, I-00133 Rome, Italy|Tech Univ Madrid, Ctr Biomed Technol, Lab Cognit & Computat Neurosci UCM UPM, Madrid, Spain;
Leaky Integrate-and-Fire with Latency (LIFL); Neuron; Synapse; STDP; Memristor; Neuromorphic system; Analog VLSI;
机译:用于STDP的神经元和忆阻突触的高效混合CMOS纳米电路设计
机译:Memristive Synapse连接的Chay双神经元网络和硬件实现的同步行为
机译:基于神经元和突触模型的四足运动硬连线中央模式发生器硬件网络
机译:忆阻突触的行为建模和STDP学习特征
机译:使用忆阻突触和纳米晶体硅薄膜晶体管的人工神经系统
机译:在尖峰神经网络中通过STDP进行统计学习的复合忆阻突触模型
机译:具有忆阻性STDP突触的潜伏神经元模型的LIF的硬件设计
机译:利用硬件在环仿真中的实验设计模拟小Uas中声学特征简化的姿态方差。