首页> 外文期刊>Instrumentation and Measurement, IEEE Transactions on >Derivation and Design of In-Loop Filters in Phase-Locked Loop Systems
【24h】

Derivation and Design of In-Loop Filters in Phase-Locked Loop Systems

机译:锁相环系统中环路滤波器的推导和设计

获取原文
获取原文并翻译 | 示例
           

摘要

This paper addresses the concept of in-loop filters in phase-locked loop (PLL) systems. The in-loop filters are derived from an optimization perspective, and an analytical method to design the controlling parameters of a PLL with in-loop filters is also presented. Such filters can also be selected as conventional window functions in which case they can be tuned to reject certain frequency components similar to the discrete Fourier transform. In this paper, a rigorous method to introduce the concept of in-loop filters and window functions into PLL systems is presented. This method enables smoother estimation of the signal parameters such as phase angle, frequency, and amplitude in the presence of noise and harmonics. The in-loop filters can be adjusted to completely remove specific harmonics. The method is first developed for a single-phase enhanced PLL system and is then extended to three-phase PLLs including the well-known synchronous-reference-frame PLL. Simulation and experimental results are also included.
机译:本文介绍了锁相环(PLL)系统中的环路滤波器的概念。从优化的角度推导了环路滤波器,并提出了一种用于设计带有环路滤波器的PLL控制参数的分析方法。这样的滤波器也可以被选作常规的窗函数,在这种情况下,它们可以被调谐以拒绝某些频率分量,类似于离散傅里叶变换。在本文中,提出了一种严格的方法将环路滤波器和窗口函数的概念引入PLL系统。这种方法可以在存在噪声和谐波的情况下,更平滑地估计信号参数,例如相角,频率和幅度。可以调节环路滤波器以完全消除特定的谐波。该方法首先针对单相增强PLL系统开发,然后扩展到包括众所周知的同步参考帧PLL的三相PLL。仿真和实验结果也包括在内。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号