A statement based parallelizing framework for processor-in-memory architectures

摘要

It is widely known that current memory architecture is one of the bottlenecks for high-performance computers due to the increasing gap between the processor speed and memory latency. For this reason, several architectures, called intelligent memory (IRAM) or processor-in-memory (PIM), have been studied in recent years aiming to integrate the processor and memory together. A merit of PIM architecture is that the PIM chips can be used to replace the main memory chips in a workstation and act as coprocessors when main processor spawns them. This approach has been adopted by Active Page, DIVA, and FlexRAM, among others. This class of architectures provides a hierarchical hybrid multiprocessor environment: host (main) processors and memory processors. Host processor is more powerful with a deep cache hierarchies and higher latency to access memory. By contrast, memory processors are usually less powerful but with a lower latency in memory access. The major problems we address in this paper are: how to dispatch suitable tasks to these different processors in PIM by their computing power and characteristics to reduce their idle time, and how to partition the original program then execute simultaneously on these heterogeneous processors mixture. Based on our earlier work, we propose the SAGE (Statement-Analysis-Grouping-Evaluation) system to analyze the source program, generate a Weight Partition Dependence Graph (WPG), determine the weight of each block, and then dispatch the most suitable jobs to the host and memory processors, respectively. From the experiment, we find that quite good speedup is obtained, which even exceeds the computation capability ratio in 1-host and 1-memory processors environment.