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Energy efficient modular exponentiation for public-key cryptography based on bit forwarding techniques

机译:基于位转发技术的公共密钥加密的节能模块化幂运算

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Modular exponentiation and modular multiplications are two fundamental operations in various cryptographic applications, and hence the performance of public-key cryptographic algorithms is strongly influenced by the efficient implementation of these operations. Reducing the frequency of modular multiplications and the time requirements for modular multiplication will help in developing efficient modular exponential algorithms. This work proposes an energy efficient modular exponential algorithm based on bit forwarding techniques. In particular, two algorithms, Bit Forwarding 1-bit (BFW1) and Bit Forwarding 2-bits (BFW2), which are modifications of the existing binary exponential algorithm, have been developed. Hardware realizations of the proposed algorithms have been evaluated in terms of throughput, power and energy. Results show increased throughput of the order of 11.02% and 15.13%, reduction in power to 1.93% and 6.35% and energy saving of the order of 1.9% and 6.35% for BFW1 and BFW2 algorithms respectively. Xilinx ISE-14.2 on Virtex-5 evaluation board and ICARUS verilog simulation and synthesis tool are used for hardware realization for FPGA and synthesized using Cadence for ASIC. (C) 2016 Elsevier B.V. All rights reserved.
机译:模幂和模乘法是各种密码应用程序中的两个基本操作,因此,公钥密码算法的性能受这些操作的有效实现的强烈影响。减少模乘的频率和模乘的时间要求将有助于开发有效的模指数算法。这项工作提出了一种基于位转发技术的节能模块化指数算法。尤其是,已经开发了两种算法,即对现有二进制指数算法的修改的位转发1位(BFW1)和位转发2位(BFW2)。已针对吞吐量,功率和能量评估了所提出算法的硬件实现。结果表明,BFW1和BFW2算法的吞吐量分别提高了11.02%和15.13%,功耗降低到1.93%和6.35%,节能分别为1.9%和6.35%。 Virtex-5评估板上的Xilinx ISE-14.2和ICARUS verilog仿真和综合工具用于FPGA的硬件实现,并使用Cadence进行ASIC的综合。 (C)2016 Elsevier B.V.保留所有权利。

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