Voltage Balancing and Commutation Suppression in Symmetrical Cascade Multilevel Converters for Power Quality Applications

摘要

This paper presents a modulation strategy for symmetrical cascaded multilevel converters that simultaneously balances the individual DC voltages and reduces switching losses by eliminating redundant or unnecessary commutations. The voltage regulation is based on a 1-bit digital signal indicating whether the DC link voltage of each H-bridge is above or below the set point. The system command identifies commutations that can be suppressed without causing output voltage distortion, thus reducing converter losses. The voltage balancing is reached by postponing each switching commutation for a short lapse of time. Simulation and experimental results for an active filter application validate the proposed methods.