A Programmable Built-in Self-Test for Embedded Memory Cores

摘要

A memory test algorithm for detecting neighborhood pattern sensitive faults (NPSFs), including static NPSF (SNPSF), passive NPSF (PNPSF) and active NPSF (ANPSF), is proposed in this paper. The patterns can also detect all the traditional faults present in the memory array such as stuck-at faults (SAFs), transition faults (TFs), coupling faults (CFs) and address decoder faults. Next, a programmable BIST architecture is designed. The BIST circuit allows the users to select a vast variety of test algorithms based on their choice. The single BIST circuit is capable of testing different types of memory cores embedded in SOC. The proposed BIST circuit is shared among the different memory cores in an SOC. For this purpose, test wrappers for the shared BIST circuits and the memory cores are designed. Finally, a test scheduling algorithm is developed to reduce the overall test time.