Simulation of Piecewise-Linear One-Dimensional Chaotic Maps by Verilog-A

摘要

Piecewise-linear one-dimensional (PL1D) chaotic maps have simple mathematical descriptions, while their behaviour is rich and complex. This nature is ideal for the development of integrated circuit (IC) designs and applications. Moreover, one needs to determine the conditions from which PL1D maps can become chaotic. With this in mind, this article introduces the high-level behavioural simulation of PL1D chaotic maps by Verilog-A descriptions, from which one can find the values guaranteeing the conditions to maintain chaotic behaviour, and then one can synthesize the block descriptions to the transistor level of abstraction, e.g. linking simulation program with integrated circuits emphasis (SPICE) simulations. In this manner, we highlight that this can be the first step in a top-down IC design flow for the successful implementation of integrated PL1D chaotic maps.